The production test of integrated circuits constitutes a significant cost factor in the production of such integrated circuits. In order to optimize the costs arising during the production test of integrated circuits, it is often attempted to utilize the capacity of the available test apparatuses in the best possible manner. If the test algorithm with which the integrated circuits are tested is optimized for a minimum test time, all possibilities for reducing costs have already been exhausted in the case of this approach.
A further approach for testing integrated circuits consists in checking a plurality of integrated circuits simultaneously on a tester. This requires correspondingly converting the testers used, in particular adapting the load board for receiving a plurality of integrated circuits. In this case a load board is understood to be a receptacle which is used during such a test and is able to receive one or a plurality of integrated circuits to be tested. In the case of parallel tests of integrated circuits that have been carried out in this way, it has not been possible heretofore to supply the integrated circuits to be tested with the same signal level. Therefore, the results of such parallel tests of integrated circuits often have only little meaningfulness. This has the effect that in such parallel tests, inherently defect-free integrated circuits are sorted out and defective integrated circuits are deemed to be good.